Prebuilt application images are executed on the Cortex M0+ core of the PSoC 6 dual-core MCU. The images are provided as C arrays ready to be compiled as part of the Cortex M4 application. The Cortex M0+ application code is placed to internal flash by the Cortex M4 linker script.
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This image starts CM4 core at CY_CORTEX_M4_APPL_ADDR=0x10002000 and puts CM0+ core into a deep sleep mode.
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This image starts crypto server on CM0+ core, starts CM4 core at CY_CORTEX_M4_APPL_ADDR=0x10008000 and puts CM0+ core into a deep sleep mode.
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This image starts BLE controller on CM0+ core, starts CM4 core at CY_CORTEX_M4_APPL_ADDR=0x10020000 and puts CM0+ core into a deep sleep mode.
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This image starts CM4 core at address corresponding to Secure Boot policy, sets required security settings, initializes and executes code of Protected Register Access driver, puts CM0+ core into a deep sleep mode.
- CM0P_BLESS image is updated with BLESS firmware version bless-5.0.10.400
- Known Issues:
- With PSoC 6 BLE, if LE Privacy is enabled and the device resolving list (RL) is non empty, IUT as advertiser does not respond to Scan request or connect request from peers which are using Resolvable Private Address (RPA) but are not present in the RL. Workaround is to clean the resolving list and disable address resolution before starting advertisements.
- CM0P_BLESS image is updated with BLESS firmware version bless-5.0.10.347
- Known Issues: i. With ble app running in PSoC 6 BLE, when Remote Device A is bonded, Remote Device B would have scanning/connecting issues. Recovery is to delete the bonding of Remote Device A. ii. While running BLE stress test cases, some times controller stops sending HostMsgFlushRecvCallBack to HOST for the sent messages. This blocks all further operations. Recovery is to reset the board.
- Rebuilt with Peripheral Driver Library (mtb-pdl-cat1) version 2.3.1
- Rebuilt with Peripheral Driver Library (mtb-pdl-cat1) version 2.3.0
- COMPONENT_CM0P_SECURE image updated:
- Do not use default initialization, keep clocks configuration, set by Secure FlashBoot
- Add supoort for
cysecuretools 3.1.x
- Rebuild with Peripheral Driver Library (mtb-pdl-cat1) version 2.2.0.
- COMPONENT_CM0P_SECURE image updated to include:
- WDT management per policy settings
- Support swap upgrade mode in CypressBootloader
- External clocks and SRAM power modes management per policy settings
- Rebuild with Peripheral Driver Library (mtb-pdl-cat1) version 2.1.0.
- COMPONENT_CM0P_BLESS image was updated to use BLESS 3.50 Middleware library.
- Rebuilt with Peripheral Driver Library (mtb-pdl-cat1) version 2.0.0.
- Rebuilt with PSoC 6 Peripheral Driver Library (psoc6pdl) version 1.6.1.
- New secure image (COMPONENT_CM0P_SECURE)
- Rebuilt with PSoC 6 Peripheral Driver Library (psoc6pdl) version 1.6.0.
- Rebuilt with PSoC 6 Peripheral Driver Library (psoc6pdl) version 1.5.0.
- COMPONENT_CM0P_BLESS image was updated to use BLESS 3.40 Middleware library. This fixes CVE-2019-16336 and CVE-2019-17061 Vulnerabilities.
- Rebuilt with PSoC 6 Peripheral Driver Library (psoc6pdl) version 1.4.1.
- Rebuilt with PSoC 6 Peripheral Driver Library (psoc6pdl) version 1.4.0.
- COMPONENT_CM0P_BLESS image was updated to use BLESS 3.30 Middleware library
- Increased memory slot in COMPONENT_CM0P_CRYPTO from 32K to 40K
Note: This version is incompatible with PDL versions prior to 1.4.0 when using DeepSleep and UDB based SDIO.
- Initial release
To pick which image is used in an application update the COMPONENTS variable in the Board Support Package (BSP)'s makefile. Depending on which image is selected, an update to the BSPs linker script may also be required to allocate the proper space for the CM0+ image and that the CM4 has the starting address listed above.
This version of the (PSoC 6 Cortex M0+ prebuilt images) was validated for compatibility with the following Software and Tools:
| Software and Tools | Version |
|---|---|
| GCC Compiler | 7.4 |
| IAR Compiler | 8.32 |
| ARM Compiler 6 | 6.11 |
Use the following links for more information, as needed:
Copyright (c) Cypress Semiconductor Corporation, 2020.