EZ-USB™ FX20: Slave FIFO 2-bit application

This code example demonstrates the implementation of LVCMOS to USB data transfer application using a 2-bit Slave FIFO interface on the EZ-USB™ FX20 device. This example illustrates the configuration and usage of Sensor Interface Port (SIP) on the EZ-USB™ FX20 device to receive multiple streams of data and forward them on separate USB endpoints.

Note: This code example is also applicable to EZ-USB™ FX10, EZ-USB™ FX5N, and EZ-USB™ FX5 devices.

View this README on GitHub.

Provide feedback on this code example.

Requirements

ModusToolbox™ v3.4 or later (tested with v3.4)
Board support package (BSP) minimum required version: 4.3.3
Programming language: C

Supported toolchains (make variable 'TOOLCHAIN')

GNU Arm® Embedded Compiler v11.3.1 (GCC_ARM) – Default value of TOOLCHAIN
Arm® Compiler v6.22 (ARM)

Supported kits (make variable 'TARGET')

EZ-USB™ FX20 DVK (KIT_FX20_FMC_001) – Default value of TARGET

Hardware setup

This example uses the board's default configuration. See the kit user guide to ensure that the board is configured correctly.

The Titanium Ti180 J484 Development Kit is used to drive the LVCMOS interface on the FX20 device based on the Synchronous Slave FIFO protocol. The FMC connector (J8) on the FX20 DVK should be connected to the FMC connector on the J484 board while running the application.

Software setup

See the ModusToolbox™ tools package installation guide for information about installing and configuring the tools package.

Install a terminal emulator if you do not have one. Instructions in this document use Tera Term
Install the EZ-USB™ FX Control Center application to help with device programming and testing
Install the Efinity Software from EFINIX to get the tools to program the Titanium Ti180 J484 Development Board

Using the code example

Create the project

The ModusToolbox™ tools package provides the Project Creator as both a GUI tool and a command line tool.

Use Project Creator GUI

Open the Project Creator GUI tool

There are several ways to do this, including launching it from the dashboard or from inside the Eclipse IDE. For more details, see the Project Creator user guide (locally available at {ModusToolbox™ install directory}/tools_{version}/project-creator/docs/project-creator.pdf)
On the Choose Board Support Package (BSP) page, select a kit supported by this code example. See Supported kits

Note: To use this code example for a kit not listed here, you may need to update the source files. If the kit does not have the required resources, the application may not work
On the Select Application page:

a. Select the Applications(s) Root Path and the Target IDE

Note: Depending on how you open the Project Creator tool, these fields may be pre-selected for you

b. Select this code example from the list by enabling its check box

Note: You can narrow the list of displayed examples by typing in the filter box

c. (Optional) Change the suggested New Application Name and New BSP Name

d. Click Create to complete the application creation process

Use Project Creator CLI

The 'project-creator-cli' tool can be used to create applications from a CLI terminal or from within batch files or shell scripts. This tool is available in the {ModusToolbox™ install directory}/tools_{version}/project-creator/ directory.

Use a CLI terminal to invoke the 'project-creator-cli' tool. On Windows, use the command-line 'modus-shell' program provided in the ModusToolbox™ installation instead of a standard Windows command-line application. This shell provides access to all ModusToolbox™ tools. You can access it by typing "modus-shell" in the search box in the Windows menu. In Linux and macOS, you can use any terminal application.

The following example clones the "mtb-example-fx20-slave-fifo-2bit" application with the desired name "Slave_FIFO_2Bit" configured for the KIT_FX20_FMC_001 BSP into the specified working directory, C:/mtb_projects:

project-creator-cli --board-id KIT_FX20_FMC_001 --app-id mtb-example-fx20-slave-fifo-2bit --user-app-name Slave_FIFO_2Bit --target-dir "C:/mtb_projects"

The 'project-creator-cli' tool has the following arguments:

Argument	Description	Required/optional
`--board-id`	Defined in the field of the BSP manifest	Required
`--app-id`	Defined in the field of the CE manifest	Required
`--target-dir`	Specify the directory in which the application is to be created if you prefer not to use the default current working directory	Optional
`--user-app-name`	Specify the name of the application if you prefer to have a name other than the example's default name	Optional

Note: The project-creator-cli tool uses the git clone and make getlibs commands to fetch the repository and import the required libraries. For details, see the "Project creator tools" section of the ModusToolbox™ tools package user guide (locally available at {ModusToolbox™ install directory}/docs_{version}/mtb_user_guide.pdf).

Open the project

After the project has been created, you can open it in your preferred development environment.

Eclipse IDE

If you opened the Project Creator tool from the included Eclipse IDE, the project will open in Eclipse automatically.

For more details, see the Eclipse IDE for ModusToolbox™ user guide (locally available at {ModusToolbox™ install directory}/docs_{version}/mt_ide_user_guide.pdf).

Visual Studio (VS) Code

Launch VS Code manually, and then open the generated {project-name}.code-workspace file located in the project directory.

For more details, see the Visual Studio Code for ModusToolbox™ user guide (locally available at {ModusToolbox™ install directory}/docs_{version}/mt_vscode_user_guide.pdf).

Command line

If you prefer to use the CLI, open the appropriate terminal, and navigate to the project directory. On Windows, use the command-line 'modus-shell' program; on Linux and macOS, you can use any terminal application. From there, you can run various make commands.

For more details, see the ModusToolbox™ tools package user guide (locally available at {ModusToolbox™ install directory}/docs_{version}/mtb_user_guide.pdf).

Operation

Connect the board (J2) to your PC using the provided USB cable. Connect the USB FS port (J3) on the board to the PC for debug logs
Open a terminal program and select the serial COM port. Set the serial port parameters to 8N1 and 921600 baud
Connect the FPGA (Titanium Ti180 J484 Development Kit) DVK to the FMC (J8) connector of KIT_FX20_FMC_001 board
Browse the <CE Title>/BitFiles/ folder for Ti180 FPGA binary and program the FPGA. For more details, see the J484 kit user guide
Perform the following steps to program the board using the EZ-USB™ FX Control Center (Alpha) application
1. To enter into Bootloader mode:
  
  a. Press and hold the PMODE (SW2) switch
  b. Press and release the RESET (SW3) switch
  c. Finally, release the PMODE switch
2. Open the EZ-USB™ FX Control Center application
  The EZ-USB™ FX20 device enumerates as EZ-USB™ FX Bootloader
3. Select the EZ-USB™ FX Bootloader device in EZ-USB™ FX Control Center
4. Click Program > Internal Flash
5. Navigate to the <CE Title>/build/APP_KIT_FX20_FMC_001/Release folder within the CE directory and locate the .hex file and program
  Confirm if the programming is successful in the log window of the EZ-USB™ FX Control Center application
After programming, the application starts automatically. Confirm that the following title is displayed on the UART terminal

Figure 1. Terminal output on program startup
Using the EZ-USB™ FX Control Center application, go to the Performance Measurement tab and select the Endpoints 0x81, 0x82, 0x83, and 0x84 in round robin fashion. Click Start to start the data transfer and click Stop when errors are reported. Then, move to the next endpoint in the round robin way and repeat the data transfers
The device sends 16.5 MB (16,588,800 bytes) of data on each endpoint before it moves to the next endpoint. Use the Control Center application to read the data available on each endpoint before moving forward to the next one

Debugging

Using Arm® debug port

If you have access to a MiniProg or KitProg3 device, you can debug the example to step through the code.

In Eclipse IDE

Use the <Application Name> Debug (KitProg3_MiniProg4) configuration in the Quick Panel. For details, see the "Program and debug" section in the Eclipse IDE for ModusToolbox™ user guide.

In other IDEs

Follow the instructions in your preferred IDE.

Log messages

The code example and the EZ-USB™ FX20 stack output debug log messages indicates any unexpected conditions and highlights the operations performed.

By default, the USB FS port is enabled for debug logs. To enable debug logs on UART, set the USBFS_LOGS_ENABLE compiler flag to '0u' in the Makefile. SCB1 of the EZ-USB™ FX20 device is used as UART with a baud rate of 921600 to send out log messages through the P8.1 pin.

The verbosity of the debug log output can be modified by setting the DEBUG_LEVEL macro in main.c file with the values shown in Table 1.

Table 1. Debug values

Macro value	Description
1u	Enable only error messages
2u	Enable error and warning messages
3u	Enable info messages
4u	Enable all message types

Design and implementation

This code example demonstrates the implementation of the Synchronous Slave FIFO protocol with 2-bit addressing on the LVCMOS interface of the EZ-USB™ FX20 device. As 2-bit addressing is used, the FPGA master can access four different FIFOs on the EZ-USB™ FX20 device and write data into them. The data received on each of these FIFO is forwarded by the EZ-USB™ FX20 to the USB host over a different USB Bulk-IN endpoint.

Note: Though the Slave FIFO protocol allows bidirectional data transfers, this application only supports data transfers from the FPGA into the EZ-USB™ FX20 device and then to the USB interface.

In addition to the LVCMOS and USB interfaces, this application uses the following low-performance peripherals to interface with the system:

Serial Communication Block (SCB0) is used in I2C Master mode to configure and enable/disable the data stream from the FPGA
Serial Memory Interface (SMIF) is used in x4 or Quad mode to configure the FPGA device in Passive Serial mode on every boot-up
Debug logs from the application are output using either the Full-Speed USB debug port (J3) or using SCB1 in UART mode

Features

This code example demonstrates the following capabilities of the EZ-USB™ FX20 device:

The usage of the EZ-USB™ FX20 APIs to implement a vendor-specific USB device capable of operating up to 20 Gbps speeds
The usage of the EZ-USB™ FX20 APIs to implement a Synchronous Slave FIFO interface to receive multiple streams of data from an FPGA master
FPGA configuration using SMIF Block of the EZ-USB™ FX20 device
I2C accesses to configure the FPGA data generator through a register interface

Streaming data path

The application enables four EPs IN (1-IN, 2-IN, 3-IN, and 4-IN) as Bulk endpoints with maximum packet size of 1024 bytes. In case of USB 3.2 operation, the endpoints are configured to support maximum burst of 16 packets each.
The Sensor Interface Port (SIP) on EZ-USB™ FX20 is configured as a WideLink LVCMOS port with 32-bit wide data bus
Four threads are used to receive separate streams of data from the FPGA. Two bits of address are used to select the thread for data transfer. Each thread is mapped to a single socket in the DMA adapter, which is then connected to a different USB endpoint. The mapping of FIFO address to the thread, socket, and USB endpoint is shown in Table 2

Table 2. FIFO address to thread, socket, and endpoint mapping

FIFO address GPIF thread SIP Socket USB endpoint

'b00 Thread-0 Socket 0 1-IN

'b01 Thread-1 Socket 1 2-IN

'b10 Thread-2 Socket 2 3-IN

'b11 Thread-3 Socket 3 4-IN

The SIP sockets are connected to the USB endpoints using high bandWidth DMA channels, which use two RAM buffers of 63 KB (64512 bytes) each. The DMA channels are configured as auto channels with no firmware intervention required during the data transfer

Application workflow

The application flow involves three main steps:

Initialization
USB device enumeration
Data transfer

Initialization

During initialization, the following steps are performed:

All the required data structures are initialized
USBD and USB driver (CAL) layers are initialized
Application registers all descriptors supported by function/application with the USBD layer
Application registers callback functions for different events, such as RESET, SUSPEND, RESUME, SET_CONFIGURATION, SET_INTERFACE, SET_FEATURE, and CLEAR_FEATURE. USBD will call the respective callback function when the corresponding events are detected
Initialize the data transfer state machines
Application registers handlers for all relevant interrupts
Application makes the USB device visible to the host by calling the connect API
FPGA is configured using the SMIF (in x4 or Quad mode) block to read the bit file stored in the external flash. FPGA sees the data on the bus and gets configured
FPGA is initialized using I2C writes to FPGA registers
Application initializes the SIP block on the EZ-USB™ FX20 as required by the selected LVCMOS operating mode
If the LVCMOS interface is used in Dual Data Rate (DDR) mode, the LINK_READY pin is asserted HIGH to let the FPGA know that the link training pattern should be driven on the data bus
EZ-USB™ FX20 device and FPGA are ready for data transfers

USB device enumeration

During USB device enumeration, the host requests for descriptors, which are already registered with the USBD layer during the initialization phase
Host will send SET_CONFIGURATION and SET_INTERFACE commands to activate the required function in the device
As part of the SET_CONFIGURATION handler, the application creates and enables all DMA channels that move the data from the LVCMOS interface to the USB endpoints

Data transfer

After enabling the streaming DMA channels, the DMA ready flag on the SIP interface asserts indicating that the device is ready to receive data from the FPGA.
The FPGA data source starts sending data to each of the FIFOs (threads) in a round-robin way. The 16588800 bytes of data (equivalent to one YUY2 video frame with 4K resolution) are sent to each FIFO before the FPGA moves to the next one
Data moves from the LVCMOS subsystem to SRAM through high-bandwidth DMA
The data is forwarded on the USB 3.2 or USB 2.1 endpoints, based on the active USB connection speed. DataWire DMA channels are used in the case of USB 2.1 transfers and high-bandwidth DMA channels are used in case of USB 3.2 transfers

Slave FIFO interface

The code example uses a Synchronous Slave FIFO interface with 2-bit addressing. The Slave FIFO interface connections are as follows:

Table 3. Control signal usage in LVCMOS Slave FIFO state machine for PORT0 in WideLink mode

EZ-USB™ FX pin	Function	Description
P0CLK	PCLK	LVCMOS clock input
P0CTL0	SLCS#	Active Low Chip Select signal. Assert by FPGA when communicating with EZ-USB™ FX20
P0CTL1	SLWR#	Active Low Write Enable signal. Assert by FPGA when sending data to EZ-USB™ FX20
P0CTL2	SLOE#	Active Low Output Enable signal. Not used in this application and expected to be driven HIGH by FPGA
P0CTL3	SLRD#	Active Low Read Enable signal. Not used in this application and expected to be driven HIGH by FPGA
P0CTL5	FlagA	Active Low DMA ready indication for currently addressed (active) thread
P0CTL6	LINK_READY	Active High Link ready indication from EZ-USB™ FX20 to FPGA. Used to trigger link training sequence in DDR mode
P0CTL7	PKTEND#	Active Low Packet End signal. Assert if FPGA wants to terminate the ongoing data transfer
P1CTL9	A0	LS bit of 2-bit address bus used to select thread
P1CTL8	A1	MS bit of 2-bit address bus used to select thread

FPGA configuration

Configure the Ti180 FPGA after each power-up using the data stored in the flash on the J484 kit. The configuration of the FPGA is controlled by the EZ-USB™ FX20 device. EZ-USB™ FX20 uses its Serial Memory Interface (SMIF) in x4 or Quad mode to read the configuration data from the flash memory. As the FPGA is configured in the Passive Serial x4 mode for configuration, it will take the data presented on its pins and configure itself.

Steps to configure FPGA in Passive Serial x4 mode:

EZ-USB™ FX device deasserts INT_RESET pin
EZ-USB™ FX device starts sending a dummy SMIF (in x4 or Quad mode) clock to read the FPGA bitfile from SPI flash
FPGA listens to the data on the SMIF lines and configures itself
FPGA asserts CDONE# pin when configuration is complete

Table 4. EZ-USB™ FX20 GPIOs used during FPGA configuration

EZ-USB™ FX pin	Function	Description
P4.3	INIT_RESET#	Active Low signal used by EZ-USB™ FX20 device to reset the Ti180 FPGA
P6.4	PROG#	Active Low FPGA program signal. Assert by EZ-USB™ FX20 before initiating read from QSPI flash memory
P4.4	CDONE	Active High Configuration Done signal asserted by FPGA when it is fully initialized

Compile-time configurations

Application functionality can be customized by setting variables in Makefile or by configuring them through make CLI arguments.

Run the make build command or build the project in your IDE to compile the application and generate a USB bootloader-compatible binary. This binary can be programmed onto the EZ-USB™ FX20 device using the EZ-USB™ Control Center application
Run the make build BLENABLE=no command or set the variable in Makefile to compile the application and generate the standalone binary. This binary can be programmed onto the EZ-USB™ FX20 device through the SWD interface using the OpenOCD tool. For more details, see the EZ-USB™ FX20 SDK user guide
Choose between the Arm® Compiler or the GNU Arm® Embedded Compiler build toolchains by setting the TOOLCHAIN variable in Makefile to ARM or GCC_ARM respectively. If you set it to ARM, ensure to set CY_ARM_COMPILER_DIR as a make variable or environment variable, pointing to the path of the compiler's root directory

By default, the application is configured to receive data from a 32-bit wide LVCMOS interface in DDR mode and make a USB 3.2 Gen2x2 (20 Gbps) data connection. Additional settings can be configured through macros specified by the DEFINES variable in Makefile:

Table 5. Macro description

Macro name	Description	Allowed values
USB_CONN_TYPE	Choose USB connection speed from amongst a set of options	'`CY_USBD_USB_DEV_SS_GEN2X2`' for USB 3.2 Gen2x2 '`CY_USBD_USB_DEV_SS_GEN2`' for USB 3.2 Gen2x1 '`CY_USBD_USB_DEV_SS_GEN1X2`' for USB 3.2 Gen1x2 '`CY_USBD_USB_DEV_SS_GEN1`' for USB 3.2 Gen1x1 '`CY_USBD_USB_DEV_HS`' for USB 2.0 HS '`CY_USBD_USB_DEV_FS`' for USB 1.1 FS
LVCMOS_DDR_EN	Selects the LVCMOS interface data rate	'1u' to select Dual Data Rate operation '0u' to select Single Data Rate operation
USBFS_LOGS_ENABLE	Enable debug logs through USB FS port	'1u' to enable logging through debug USBFS port '0u' to enable logging through UART (SCB1)

FPGA BitFile information

The bitfiles required to drive the LVCMOS interface on the EZ-USB™ FX20 device from the Ti180 FPGA are provided in the BitFile folder of this code example. These bitfiles need to be programmed onto the flash devices in the Titanium Ti180 J484 kit using the Efinity Software.

Table 6. BitFile description

BitFile name	Description
fxn_ti180_dvk_multi_cam_ref_des_lvcmos_148m_ddr_u3v_features_working.hex	Implements FIFO master functionality for LVCMOS DDR mode
fxn_ti180_dvk_multi_cam_ref_des_lvcmos_sdr_wl.hex	Implements FIFO master functionality for LVCMOS SDR mode

Application files

Table 7. Application file description

File	Description
cy_gpif_header.h	Generated header file for GPIF state configuration of LVCMOS interface
cy_usb_app.c	C source file implementing Slave FIFO application logic
cy_usb_app.h	Header file for application data structures and functions declaration
cy_usb_descriptors.c	C source file containing the USB descriptors
main.c	Source file for device initialization, ISRs, LVCMOS interface initialization, etc.
cy_usb_i2c.c	C source file with I2C handlers
cy_usb_i2c.h	Header file with I2C application constants and the function definitions
cy_usb_qspi.c	C source file with SMIF handlers and FPGA configuration functions
cy_usb_qspi.h	Header file with SMIF application constants and the function definitions
cm0_code.c	Binary code block to be run by the Cortex®-M0 Plus core to start the Cortex®-M4 core
Makefile	GNU make compliant build script for compiling this example

Related resources

Resources	Links
Application notes	AN237841 – Getting started with EZ-USB™ FX20/FX10/FX5N/FX5
Code examples	Using ModusToolbox™ on GitHub
Device documentation	EZ-USB™ FX20 datasheets
Development kits	Select your kits from the Evaluation board finder
Libraries on GitHub	mtb-pdl-cat1 – Peripheral Driver Library (PDL)
Middleware on GitHub	usbfxstack – USBFX Stack middleware library and docs
Tools	ModusToolbox™ – ModusToolbox™ software is a collection of easy-to-use libraries and tools enabling rapid development with Infineon MCUs for applications ranging from wireless and cloud-connected systems, edge AI/ML, embedded sense and control, to wired USB connectivity using PSOC™ Industrial/IoT MCUs, AIROC™ Wi-Fi and Bluetooth® connectivity devices, XMC™ Industrial MCUs, and EZ-USB™/EZ-PD™ wired connectivity controllers. ModusToolbox™ incorporates a comprehensive set of BSPs, HAL, libraries, configuration tools, and provides support for industry-standard IDEs to fast-track your embedded application development

Other resources

Infineon provides a wealth of data at www.infineon.com to help you select the right device, and quickly and effectively integrate it into your design.

Document history

Document title: CE241358 – EZ-USB™ FX20: Slave FIFO 2-bit application

Version	Description of change
1.0.0	New code example

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